From: Lukáš Jiřiště Date: Mon, 19 Feb 2024 21:40:29 +0000 (+0100) Subject: Add samples of logic gates X-Git-Url: https://git.ljiriste.work/?a=commitdiff_plain;h=a698cb3389ef2e93f5eaaad85d0214e762601110;p=FET_sim.git Add samples of logic gates --- diff --git a/samples/NOT b/samples/NOT new file mode 100644 index 0000000..c47fa42 --- /dev/null +++ b/samples/NOT @@ -0,0 +1,6 @@ +addfet p +addnode pull_up +addnode off 2 +bind 0 0 source +bind 1 0 gate +bind 2 0 drain diff --git a/samples/nopull_NAND b/samples/nopull_NAND new file mode 100644 index 0000000..4e96452 --- /dev/null +++ b/samples/nopull_NAND @@ -0,0 +1,17 @@ +addfet n 2 +addfet p 2 +addnode off 3 +addnode on +addnode float 2 +bind 0 0 gate +bind 0 2 gate +bind 1 1 gate +bind 1 3 gate +bind 3 0 source +bind 3 1 source +bind 4 0 drain +bind 4 1 drain +bind 4 2 source +bind 5 2 drain +bind 5 3 source +bind 2 3 drain diff --git a/samples/nopull_NOT b/samples/nopull_NOT new file mode 100644 index 0000000..a35a6bb --- /dev/null +++ b/samples/nopull_NOT @@ -0,0 +1,11 @@ +addfet n +addfet p +addnode on +addnode float +addnode off 2 +bind 0 0 source +bind 1 0 drain +bind 2 0 gate +bind 1 1 source +bind 2 1 gate +bind 3 1 drain