I mostly wanted to add the optimization idea.
come up with better file structure
implement circuit builder that converts circuit language to FET_sim representation in order to simulate
- mostly done
+somehow solve the graphics of circuits loaded from a file
Group nodes and mosfets in a "graph" structure
add even more simulation commands(eg. delete node/fet)
test the project
improve simulator io (maybe add graphics?)
optimize
+ - during simulation step note mosfets whose gate state has changed, next step only go through drain and source nodes of these fets
pass 42 norminette
+ - is it worth it anymore? Strive for nice code ofcourse.
DONE
rewrite t_fet and t_node to store indexes insted of pointers to connected parts