projects / FET_sim.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: b3ac704) | patch
Add samples of logic gates
authorLukáš Jiřiště <gymnazium.jiriste@gmail.com>
Mon, 19 Feb 2024 21:40:29 +0000 (22:40 +0100)
committerLukáš Jiřiště <gymnazium.jiriste@gmail.com>
Mon, 19 Feb 2024 21:40:29 +0000 (22:40 +0100)
commita698cb3389ef2e93f5eaaad85d0214e762601110
treea84b681a0c4bed8cd963e71990c187592853ee10tree | snapshot (zip tar.gz)
parentb3ac7043a4a31a4b6eccf60e2e4ea2877c4088ffcommit | diff
Add samples of logic gates
samples/NOT [new file with mode: 0644] blob
samples/nopull_NAND [new file with mode: 0644] blob
samples/nopull_NOT [new file with mode: 0644] blob
Unnamed repository; edit this file 'description' to name the repository.